Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design.

Provide technical support to customers via telephone and other electronic means, and at customer locations Assist customers in deploying Siemens EDA's Questa to solve design challenges Track and update customer issues using defined Siemens EDA's processes and tracking tools Develop and deliver technical training on new features and product updates Develop technical content for Siemens EDA's knowledge base Communicate customers' technical requirements as well as customer issues to the product and sales teams Work collaboratively with team members to ensure mutual success

[Qualifications] • More than 5 years experiences related with register-transfer-level (RTL) & GLS(Gate-Level Simulation) digital logic design, functional verification methodology, static verification, and FPGA & emulation a plus • Bachelor’s degree in EE and related field required Strong written and oral communications in the English language is a plus • Build strong rapport and credibility with customer organizations while maintaining a company internal network of contacts • With strong communications and interpersonal skills [This experience should include some of the followings] • Job Experience Requirement - Verification of Full SoC and IP level : Verilog RTL/GLS simulation is must, Validation of IP on FPGA platform is a plus - Familiar with SystemVerilog, UVM is must - SOC work & verification with ARM Cores, protocols like AXI, ACE, APB ... a plus - Familiar with mobile AP, memory spec. like DDR, LPDDR, HBM is a plus • Tool Experience - Design and Simulation in RTL/GLS : Verilog-HDL, SystemVerilog, Questa, NC-Verilog, Xcelium, VCS - RTL Debugger: Visualizer, DVE, Verdi, Simvision, Verisium Debug - Logic Synthesis : Design Complier is a plus - Power verification : Power Pro, Spyglass Power, UPF flow verification is a plus

- System Verilog, OVM/UVM, PSS, SVA - SystemC, C/C++, Tcl/TK, PERL, Java, Python as a plus - Synthesis, Formal Verification, CDC/RDC/Lint and Static timing analysis as a plus