Qualcomm is a company of inventors that unlocked edge AI and connected computing ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform edge AI and connected computing potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.

Develop and optimize 3D DRAM bank organization and near-memory computing architectures to achieve high density, high TOPS/mm2, and high TOPS/W Develop and validate models for 3D DRAM performance, power, and yield as function of bank, TSV, and power distribution choices Develop novel fabrics for best/robust distribution of high-bandwidth data from 3D DRAM memory arrays to the near-memory computing units across various workloads for mobile, compute, and XR applications Develop power distribution topology that enable robust DRAM operation in the 3D stack Simulate and emulate system performance of 3D DRAM architecture choices across AI, compute, and mobile workloads Floorplan 3D DRAM chips and design memory array control structures under 3D integration manufacturing constraints, testability, repairability, and high performance

Experience in ASIC design, mixed-signal design, and performance modeling Good knowledge of memory architecture, buses, and 2.5D/3D integration Proficiency in use of EDA tools, Matlab, and Phyton Master's or Ph.D. in Electrical Engineering, Computer Science, or a related field

Experience in circuit and system design to be able to model and optimize dataflow Experience in DRAM architecture performance assessment Experience in memory circuit design (SRAM/DRAM/Flash/ROM/OPT, etc) Experience in programming language (C/C++/Phyton) or scripting language (Perl/Python) Ability to develop Verilog/Verilog-A/Verilog-AMS models of critical dataflow is strong plus Familiar with the DRAM datasheets and IO interfaces

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