글로벌 선도 반도체 IP 및 실리콘 솔루션 기업에서 FAE (Applications Principal Engineer / Manager) 를 채용중에 있습니다. 많은 지원 바랍니다.

Provide technical support to customers integrating DesignWare USB Mixed Signal PHY IP as the primary focus, from initial integration through silicon bring-up and debug Troubleshoot customer issues across synthesis, static timing analysis, design-for-test, and clock domain crossing in USB PHY and SoC integration contexts Guide customers through USB 2.0, USB 3.x, and Type-C implementation considerations and design tradeoffs, and help define bring-up and debug plans that reduce time-to-silicon Collaborate closely with the Korea AE team and R&D and product teams to escalate complex issues, drive root-cause analysis, and ensure timely closure during critical milestones In addition to USB, contribute to customer support coverage for other high-speed interface PHY IP in collaboration with colleagues, leveraging similar integration and debug fundamentals (e.g., MIPI, PCIe, HDMI, etc.; excluding DDR) Deliver technical presentations and integration best practices to customer engineering teams during design reviews and key program checkpoints Travel occasionally to customer sites across Korea and the region to support critical milestones The Impact You Will Have Enable customer success on high-stakes tapeouts by resolving USB PHY integration issues that would otherwise delay schedules Reduce time-to-silicon by providing clear, actionable guidance during integration, constraints closure, and silicon bring-up Build deep technical relationships with leading semiconductor companies in Korea as their trusted advisor Shape future IP releases by channeling real customer pain points back into the product team Expand Our footprint in customer accounts through technical depth, responsiveness, and cross-team collaboration

Bachelor's or Master's in Electrical Engineering or Computer Engineering with 15 to 20+ years of ASIC design, verification, or SoC integration experience Strong working knowledge of synthesis, static timing analysis, design-for-test, and clock domain crossing Ability to work independently and drive ambiguous, customer-driven issues to resolution Excellent communication skills in Korean and English, able to explain complex concepts clearly USB 2.0, USB 3.x, Type-C, or USB PHY integration experience is a strong plus Broader high-speed interface background (e.g., MIPI, PCIe, HDMI) is a plus and helps with collaborative cross-IP support coverage Willingness to travel occasionally within Korea and the region

1차 서류전형 2차 면접전형