시스템반도체 PI/PD Engineer

• 1. PD(Physical Design)  주요업무 • Full-chip Physical Design (Floorplan, P&R, CTS) for advanced SoCs • Timing, Power, and Physical Verification closure (STA/IR/EM/DRC/LVS) • Low power design implementation and verification (UPF/CPF) • Design flow development using scripting (Python, TCL) • Technical leadership and mentorship in complex design environments  자격요건 • 3+ years of experience in ASIC Backend/Physical Design • Proficient in Synopsys (ICC2, Fusion Compiler, PrimeTime) or Cadence (Innovus, Tempus) • Hands-on experience with advanced nodes (10nm or below preferred) • Solid skills in Physical Design, STA, low power methodology, and scripting (Python/TCL/Perl) • Preferred: Experience in large-scale SoC, strong communication and problem-solving skills • •

• 2. PI(Physical Impementation)  주요업무 • DFT Implementation • SCAN insertion / ATPG / Scan Simulation (Test Compiler / TetraMax) • BIST/BIRA Insertion & Simulation (Tessent MBIST / JTAG / IJTAG) • SDC Creation & Cleanup • Spyglass LINT/SDC/DFT Checks • Logic Synthesis (DC/DCT/DCG) • Equivalence Checking (Formality / Conformal) • LDRC - Logic Design Rule Check (Spyglass_LDRC) • STA (Static Timing Analysis) & Timing Closure (Prime_Time, Physical-aware ECO) • Low Power Design (UPF, Power Gating, Clock Gating, Multi-voltage domains) • Power Analysis (Vectored / Vectorless, PTPX) • Simulator & Debugger: VCS / NC-verilog / Verdi  자격요건 • 3+ years of experience in ASIC Frontend / Physical Implementation • Understanding of SoC/ASIC design flow • Practical experience with hierarchical implementation (SYN / DFT / STA / UPF) • Hands-on skills in EDA tools, logic synthesis, and low-power implementation • Preferred: Experience in Samsung 14nm or below process 근무지 : 분당 판교 워드 국문 이력서를

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